Low-dropout (LDO) voltage regulators have gained popularity with the growth of battery-powered equipment. Portable electronic equipment including cellular telephones, pagers, laptop computers and a variety of handheld electronic devices has increased the need for efficient voltage regulation to prolong battery life. LDO voltage regulators are typically packaged as an integrated circuit (IC) to provide generally fixed output voltages over varying loads with minimal voltage dropout on the output in a battery-powered device. Furthermore, performance of LDO voltage regulators is optimized by taking into consideration standby and quiescent current flow, and stability of the output voltage.
FIG. 1 is a schematic diagram of a conventional LDO voltage regulator 100 including a startup circuit 105, a curvature corrected bandgap circuit 110, an error amplifier 115, a metal oxide semiconductor (MOS) pass device 120, (e.g., a positive channel MOS (PMOS) pass device, a negative channel MOS (NMOS) pass device), resistors 125, 130, and a decoupling capacitor 135 having a capacitance COUT. The LDO voltage regulator 100 outputs an output voltage, Vout, 145.
The curvature corrected bandgap circuit 110 is electrically coupled to the startup circuit 105 and the error amplifier 115. The startup circuit 105 provides the curvature corrected bandgap circuit 110 with current when no current is flowing through the LDO voltage regulator 100 during a supply increase or startup phase until the bandgap voltage is high enough to allow the curvature corrected bandgap circuit 110 to be self-sustaining. The curvature corrected bandgap circuit 110 generates a reference voltage 152 which is input to a positive input 150 of the error amplifier 115, and a reference current 154 which is input to a reference current input 158 of the error amplifier 115. Generally, the reference current 154 is a proportional to absolute temperature (PTAT) current generated by the curvature corrected bandgap circuit 110.
The error amplifier 115 includes a positive input 150 coupled to the curvature corrected bandgap circuit 110 for receiving the reference voltage 152, a reference current input 158 for receiving the reference current 154, a negative input 155, and an amplifier output 160.
The MOS pass device 120 includes a gate node 165, a source node 170 and a drain node 175. The MOS pass device 120 may be either a PMOS or an NMOS pass device. The gate node 165 of the MOS pass device 120 is coupled to the amplifier output 160 of the error amplifier 115. The source node 170 of the MOS pass device 120 is coupled to a supply voltage, Vs. The drain node 175 of the MOS pass device 120 generates the output voltage, Vout, 145 of the LDO voltage regulator 100. The resistors 125 and 130 are connected in series to form a resistor bridge. One end of the resistor 125 is coupled to the drain node 175 of the MOS pass device 120 and the other end of the resistor 125 is coupled to both the negative input 155 of the error amplifier 115 and one end of the resistor 130. Thus an error correction loop 180 is formed. The other end of resistor 130 is coupled to ground. The decoupling capacitor 135 is coupled between Vout and ground.
In the conventional LDO voltage regulator 100, a capacitance CMOS associated with the gate node 165 of the MOS pass device 120 and the decoupling capacitor 135 cause the slew rate and bandwidth of the error amplifier 115 to be limited. The conventional LDO voltage regulator 100 provides a fixed output voltage, but is constrained by others specifications such as voltage drop, gain and transient response. When a current step occurs, (due to the load of a circuit coupled to the output voltage, Vout, 145), the output voltage, Vout, 145 decreases first and, after an error correction loop delay Tfb occurs, the gate node 165 of the MOS pass device 120 is adjusted by the error amplifier 115 to provide the requested output current.
FIG. 2 shows a graphical representation of the output voltage, Vout, 145 of the conventional LDO voltage regulator 100 shown in FIG. 1 during a maximum current step required by the load of a circuit coupled to the voltage output, Vout, 145. The delay Tfb corresponds to the minimum error correction loop delay to ensure voltage regulation. This delay is proportional to the bandwidth of the error amplifier 115 and may be calculated in accordance with the following Equation (1):
                              Tfb          =                      1            fu                          ;                            Equation        ⁢                                  ⁢                  (          1          )                    where Tfb is the delay and fu is the unity gain frequency of the error amplifier 115.
The voltage drop during this delay may be approximated in accordance with the following Equation (2):
                    δV        -                                            I              max                                      C              out                                ⁢          Tfb                                    Equation        ⁢                                  ⁢                  (          2          )                    where δ V is the voltage drop, Imax is the maximum output current required by the load of a circuit coupled to the voltage output, Vout, 145, Cout is the capacitance of the decoupling capacitor 135 and Tfb is the error correction loop delay.
Referring to FIGS. 1 and 2, the error correction loop 180 provides voltage regulation after the Tfb delay and modifies the voltage of the gate node 165 of the MOS pass device 120 in order to switch on the MOS pass device 120. The output voltage, Vout, 145 is adjusted until the full load regulated value is reached. The time needed to recover the final value, Treg, may be approximated in accordance with the following Equation (3):
                              T          reg                =                                            C              OUT                                                      I                pass                            -                              I                max                                              ×                      V            drop                                              Equation        ⁢                                  ⁢                  (          3          )                    where Cout is the capacitance of the decoupling capacitor 135, Ipass is the current of the MOS pass device 120, Imax is the maximum output current required by the load of a circuit coupled to the voltage output, Vout, 145, and Vdrop is the maximum voltage drop.
After Treg, the voltage of the gate node 165 of the PMOS pass device 120, Vgsmax, provides sufficient current through the PMOS pass device 120 to ensure output voltage stability. However, a significant voltage drop and a delay in reaching the final regulated output voltage occurs.
It would be desirable to modify the LDO voltage regulator 100 of FIG. 1 such that it is able to more rapidly set the voltage of the gate node 165 of the PMOS pass device 120 to the Vgsmax voltage (or lower) in order to reduce output voltage drops and delays in reaching the final regulated output voltage, Vout, 145.